WiFi LoRa 32 Hardware Update Logs

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V1

• First release

• 2017-6-1 public sale

• Pinout diagram of V1

• Schematic diagram of V1

  • 433, 470~510 Version
  • 868~915 Version

 

V2

• 2018-9-15 public sale

• 4MB (32M-bits) FLASH upgrade to 8MB (64M-bits) FLASH;

• Use 40MHz HSE (V1 use 26MHz);

• Basic low power design (800uA in deep sleep);

• Add Vext power output pin, users can use this pin to drive some external device (sensor, motor etc.), when system need into deep sleep mode, Vext can be turn off.

  This pin was controlled by GPIO21, for example:

  ​ Turn ON: digitalWrite(21, LOW);

  ​ Turn OFF: digitalWrite(21, HIGH);

• Changed some pin connection:

  

• Circuit optimization, system more stable;

• Better power manage system design;

• Better RF impendence matching.

• Pinout diagram of V2

• Schematic diagram of V2

  • 433, 470~510 Version
  • 868~915 Version

 

V2.1

• 2019-6-15 public sale

• Change the RF switch from PE4259 to UPG2179, and change the RF part to the official recommended value;

• Change the power detection pin from 13(ADC2: 4) to 37(ADC1: 1).

• Pinout diagram of V2.1

• Schematic diagram of V2.1

  • 433, 470~510 Version
  • 868~915 Version