WiFi LoRa 32 Hardware Update Logs¶
2017-6-1 public sale
Schematic diagram of V1
2018-9-15 public sale
4MB (32M-bits) FLASH upgrade to 8MB (64M-bits) FLASH;
Use 40MHz HSE (V1 use 26MHz);
Basic low power design (800uA in deep sleep);
Add Vext power output pin, users can use this pin to drive some external device (sensor, motor etc.), when system need into deep sleep mode, Vext can be turn off.
This pin was controlled by GPIO21, for example:
Changed some pin connection:
Circuit optimization, system more stable;
Better power manage system design;
Better RF impendence matching.
Schematic diagram of V2